• DocumentCode
    1669891
  • Title

    A low-power multi-bit ΔΣ modulator in 90nm digital CMOS without DEM

  • Author

    Yu, Jiang ; Maloberti, Franco

  • Author_Institution
    Texas Instrum. Inc., Dallas, TX, USA
  • fYear
    2005
  • Firstpage
    168
  • Abstract
    A 2nd-order 4b ΔΣ modulator uses 3- and 5-level DAC. Truncating the ADC output while shaping and cancelling the error enables the use of low-resolution DAC and avoids DEM. The prototype is implemented in a 90nm digital CMOS technology and uses 2.1 mW from a 1.3V supply with a 40MHz clock. The SNDR is 52dB, 61dB and 72dB for an OSR of 10, 20 and 50, respectively.
  • Keywords
    CMOS digital integrated circuits; delta-sigma modulation; low-power electronics; 1.3 V; 2.1 mW; 40 MHz; 90 nm; digital CMOS; low-power ΔΣ modulator; low-resolution DAC; multi-bit ΔΣ modulator; Capacitance; Circuits; Delay; Delta modulation; Digital filters; Digital modulation; Feedback loop; Multi-stage noise shaping; Signal resolution; Transfer functions;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-8904-2
  • Type

    conf

  • DOI
    10.1109/ISSCC.2005.1493922
  • Filename
    1493922
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1669891