Title :
A 100dB SNR 2.5MS/s output data rate ΔΣ ADC
Author :
Brewer, R. ; Gorbold, J. ; Hurrell, P. ; Lyden, C. ; Maurino, R. ; Vickery, M.
Author_Institution :
Analog Devices, Newbury, UK
Abstract :
A multi-bit cascaded 2-2-0 ΔΣ modulator in 0.25μm CMOS attains 100dB SNR in a 1MHz signal bandwidth. The complete A/D converter includes an on-chip operational amplifier for driving the large input capacitors dictated by kT/C noise, a reference buffer and a programmable decimation filter. The power consumption of the modulator including reference buffer is 475mW from a dual supply (2.5V and 5V).
Keywords :
CMOS integrated circuits; analogue-digital conversion; buffer circuits; cascade networks; delta-sigma modulation; operational amplifiers; programmable filters; ΔΣ ADC; 0.25 micron; 1 MHz; 2.5 V; 475 mW; 5 V; A/D converter; CMOS; input capacitors; kT/C noise; multi-bit cascaded 2-2-0 ΔΣ modulator; on-chip operational amplifier; programmable decimation filter; reference buffer; Capacitors; Filters; Logic; Multi-stage noise shaping; Noise reduction; Noise shaping; Quantization; Sampling methods; Topology; Transfer functions;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1493924
