A novel constraint length 13 Viterbi decoder based on the iterative collapse algorithm

The system tradeoff issues of the VLSI design of a single chip constraint length 13 Viterbi decoder (VD) are addressed. All aspects of the design from the feasibility study down to the architecture of the add-compare-select (ACS) units are covered. The unifying thread that guides the development of the design is the iterative collapse algorithm (ICA) for partitioning the trellis diagram in a hierarchical fashion leadin to many diverse topologies for the VD, providing optimal tradeoffs between complexity and throughput. The development breaks down the natural boundaries of architectural tradeoffs and feasibility, memory management, design of the ACS units, and pipelining