Title :
Double-gate SOI MOSFETs with asymmetrical configuration
Author :
Allibert, F. ; Zaslavsky, A. ; Cristoloveanu, S.
Author_Institution :
Lab. de Phys. des Composants a Semicond., ENSERG, Grenoble, France
Abstract :
In this paper, we investigate additional features of performance (parasitic capacitances, switching capability etc.) and applications of slightly asymmetric DG-MOSFETs. Our simulations indicate no major disadvantages to asymmetric 50/100nm DG.
Keywords :
MOSFET; capacitance; semiconductor device models; silicon-on-insulator; 100 nm; 50 nm; Si-SiO/sub 2/; asymmetrical configuration; double-gate; double-gate SOI MOSFETs; parasitic capacitances; performance; simulations; slightly asymmetric DG-MOSFETs; switching capability; Doping; Fabrication; Land mobile radio; Logic devices; Logic testing; MOSFETs; Microelectronics; Parasitic capacitance; Transconductance; Wafer bonding;
Conference_Titel :
SOI Conference, 2001 IEEE International
Conference_Location :
Durango, CO, USA
Print_ISBN :
0-7803-6739-1
DOI :
10.1109/SOIC.2001.958030
