A VLSI sequencer chip for ATM traffic shaper and queue manager

To provide satisfactory quality of service (QOS) to all users in an asynchronous transfer mode (ATM) network, it is necessary to control the users´ traffic so that network resources, such as transmission bandwidth and buffer capacity, can be efficiently and fairly utilized by all the users while still meeting the individual QOS requirement. It is proposed that users´ traffic be controlled at two places in the network: at the user-network interface (UNI) by a traffic enforcer, and at the network-node interface (NNI) by a queue manager. Architectures for the traffic shaper and the queue manager are proposed. A key component, called the sequencer chip, to realize both architectures has been implemented, using a 1.2-μm CMOS technology. It contains about 150 k transistors, has a die size of 7.5 mm×8.3 mm, and is packaged in a 223-pin ceramic pin grid array (PGA) carrier