Hierarchical analog layout migration with pcells

Despite all the research efforts, some areas of IC design are still mainly manual, such as analog layouts. With the proliferation of systems on a chip (SoCs), the lack of efficient methods to generate analog layouts is preventing faster on-chip integration of digital and analog functionality. In this paper we propose a method that allows an efficient reuse of analog layouts between different fabrication processes. The main assumption of this work is that when designing a circuit in a new flavor or technology node, expert analog designers start by reusing a topology from an already silicon-proven circuit. If the fabrication processes are similar, then only minor adjustments in the device sizes may be needed to achieve the required performance specifications. However, different design rules might cause several small adjustments to be made. Moreover, if the source layout contains pcells, adjustments might also be needed due to small differences in the pcell sizes available in the target process. The proposed method automates these adjustments while preserving the hierarchy of the original database and re-establishes the connectivity to the target pcells, subject to the design rules of the target technology. All this is performed while maintaining the original layout topology so that the reliability of the source layout is kept in the target. An implementation of the method is discussed and results show that the connectivity is re-established in the target layouts when moving from a 0.13um node to a 90nm node, a 0.18um node and to a different 0.13um technology.