DocumentCode :
1670287
Title :
Fast and accurate behavioural simulation of fractional-N frequency synthesizer for the optimization of the lock time
Author :
Sahnoun, S. ; Fakhfakh, A. ; Masmoudi, N. ; Levi, H.
Author_Institution :
LETI Lab., Univ. of Sfax, Sfax, Tunisia
fYear :
2011
Firstpage :
1
Lastpage :
6
Abstract :
Today, the current need consisting of implementing more and more complex systems imply the implementation of new methodologies to make the CAD product reliable in order to improve time to market, study costs, reusability and reliability of the design process. This paper proposes a high level design approach applied for the simulation and the optimization of fractional-N synthesizer acting as a direct GPSK modulator and designed for the UMTS standard application. It uses the hardware description language VHDL-AMS and a genetic algorithm to optimize the modulator with a considerably reduced CPU time.
Keywords :
3G mobile communication; frequency synthesizers; genetic algorithms; hardware description languages; phase shift keying; reliability; CAD product; UMTS standard; VHDL-AMS; behavioural simulation; complex systems; direct GPSK modulator; fractional-N frequency synthesizer; genetic algorithm; hardware description language; high level design; lock time; optimization; reliability; reusability; Frequency conversion; Frequency modulation; Genetic algorithms; Optimization; Phase locked loops; Voltage-controlled oscillators; GPSK modulator; Hierarchical design; VHDL-AMS description; fractional-N synthesizer; genetic algorithm; lock time; optimization; phase noise; spurious level;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronics (ICM), 2011 International Conference on
Conference_Location :
Hammamet
Print_ISBN :
978-1-4577-2207-3
Type :
conf
DOI :
10.1109/ICM.2011.6177380
Filename :
6177380
Link To Document :
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