IVM: An interoperable verification methodology for iterative and incremental digital system design

Due to the increasing complexity of modern electronic systems, functional verification is a really hard and crucial activity to ensure the quality of digital system design. During all design phases, the verification team must deal with conflicting metrics: quality, cost and time-to-market. In order to be able to deal with this scenario and constraints, it is mandatory an efficient verification methodology to release high quality components satisfying the project´s budget and schedule. This work aims to propose a functional verification methodology that extends the considered state of art of verification methodologies (VeriSC and OVM) to support iterative and incremental development flows. The proposal includes architectural verification environment improvements and new techniques for functional coverage, which delivers an easy to implement but powerful functional coverage analysis.