Title :
BIST for strongly-indicating asynchronous circuits
Author :
Koppad, Deepali ; Efthymiou, Aris
Author_Institution :
Sch. of Inf., Univ. of Edinburgh, Edinburgh, UK
Abstract :
Testing asynchronous circuits is difficult and is one of the main reasons why these circuits are not very popular. This paper explores a test methodology for quasi-delay-insensitive circuits. It is shown that the test method proposed achieves 100% fault coverage for single stuck-at faults and also results in saving nearly 150% area overhead compared to the LSSD test approach. The method has been automated and fault coverage analysis has been performed on the ISCAS-85 benchmarks using Verifault-XL.
Keywords :
asynchronous circuits; built-in self test; failure analysis; fault diagnosis; logic testing; BIST; ISCAS-85 benchmarks; LSSD test approach; Verifault-XL; asynchronous circuit testing; fault coverage analysis; quasi-delay-insensitive circuits; strongly-indicating asynchronous circuits; stuck-at faults; test methodology; Arrays; Benchmark testing; Built-in self-test; Circuit faults; Latches; Logic gates; 100% fault coverage; Asynchronous; BIST; Datapaths;
Conference_Titel :
Very Large Scale Integration (VLSI-SoC), 2009 17th IFIP International Conference on
Conference_Location :
Florianopolis
Print_ISBN :
978-1-4577-0237-2
DOI :
10.1109/VLSISOC.2009.6041359
