A 3.1 to 5 GHz CMOS DSSS UWB transceiver for WPANs

Author

Iida, Sachio ; Tanaka, Katsuyuki ; Suzuki, Hideyuki ; Yoshikawa, Naoto ; Shoji, Norio ; Griffiths, Bernie ; Mellor, Derek ; Hayden, Frank ; Butler, Iain ; Chatwin, Jeremy

Author_Institution

Sony Corp., Tokyo, Japan

fYear

2005

Firstpage

214

Abstract

A DSSS UWB transceiver using the 3.1 to 5 GHz band is implemented in 0.18 μm CMOS and includes a programmable pulse shaping circuit in the transmitter, an LNA with a NF of 4 dB and a 6^th-order active LPF with a bandwidth of 500 MHz in the receiver. Die area of the transceiver is around 9 mm². and the transceiver consumes 105 mW in the transmit mode and 280 mW in the receive mode from a 1.8 V supply.

Keywords

CMOS analogue integrated circuits; MMIC power amplifiers; active filters; integrated circuit design; low-pass filters; personal area networks; power consumption; pulse shaping circuits; spread spectrum communication; transceivers; ultra wideband communication; 0.18 micron; 1.8 V; 105 mW; 280 mW; 3.1 to 5 GHz; 4 dB; 500 MHz; CMOS DSSS UWB transceiver; WPAN; active filters; low-pass filters; noise figure; power amplifier; programmable pulse shaping circuit; wideband LNA; wireless personal area networks; Antenna measurements; Impedance matching; Matched filters; Power amplifiers; Pulse circuits; Pulse modulation; Pulse shaping methods; Signal analysis; Spread spectrum communication; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

0-7803-8904-2

Type

conf

DOI

10.1109/ISSCC.2005.1493945

Filename

1493945