Architectural exploration of Forward 4×4 Hadamard Transform applied to H.264/AVC video compression standard

The focus of this work is the improvement of performance of the encoder of the H.264/AVC by exploiting different architectural alternatives for the Forward 4×4 Hadamard Transform. This transform module is present in the critical path for the video compression that uses intra-frame encoding in H.264/AVC standard. Combinational and sequential architectures are proposed for the calculation of the Hadamard transform algorithm. As this transform is composed by a great amount of addition operation, efficient adder compressors are used in order to achieve a higher performance in the proposed architectures. A combination of 4:2, 8:2 and 16:2 adder compressors, are used in the combinational and sequential architectures. The architectures were all described in VHDL and synthesized to TSMC 0.18μm CMOS standard cell. Synthesis results indicate that the architectures with 16:2 adder compressor reach the best performance results. While the use of this compressor enables a reduction of 17% of delay value in the combinational architecture, the frequency operation of the sequential architecture can be improved by almost 3 times, with a reduced latency, when using this adder compressor.