A dynamic reconfiguration approach for accelerating highly defective processors

The advances on the scaling process have brought several challenges concerning fault-tolerance of new technologies. At nano-scale basis, the contacts and wires defect rate is predicted to be around 1% to 15%. At this point, it will be inevitable that designs in future technologies embed some defect tolerance scheme. The desired solution at the processor level should allow the computer architecture to continue to execute software, even with the high level of defects that new technologies should introduce. This paper presents an adaptive approach that is capable of guaranteeing not only software execution but also acceleration, even under aggressive defect densities. We propose the use of an on-line binary translation mechanism implemented in a dynamically reconfigurable fabric, exploiting regularity of the reconfigurable fabric as intrinsic spare-parts, trading a small acceleration penalty for quality assurance.