Title :
A 12.5 Mb/s to 2.7 Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback
Author :
Dalton, Declan ; Chai, Kwet ; Evans, Eric ; Ferriss, Mark ; Hitchcox, Dave ; Murray, Paul ; Selvanayagam, Siva ; Shepherd, Paul ; DeVito, Larry
Author_Institution :
Analog Devices, Limerick, Ireland
Abstract :
A continuous-rate CDR (clock and data recovery) circuit is presented that operates from 12.5 Mb/s to 2.7 Gb/s. The circuit automatically detects a change in input data rate, acquires the new frequency and reports the data rate to the user without the need for an external reference clock or any programming. In tracking mode, it uses a dual-loop DLL/PLL to exceed the SONET jitter specifications.
Keywords :
BiCMOS integrated circuits; delay lock loops; frequency dividers; integrated circuit design; mixed analogue-digital integrated circuits; optical communication equipment; phase locked loops; synchronisation; voltage-controlled oscillators; 0.35 micron; 12.5 Mbit/s to 2.7 Gbit/s; BiCMOS process; SONET jitter specifications; VCO; automatic frequency acquisition; continuous-rate CDR circuit; continuous-rate clock and data recovery circuit; data-rate readback; digital divider; dual-loop DLL/PLL; external reference clock; input data rate change; tracking mode; Automatic frequency control; Clocks; Computational fluid dynamics; Detectors; Filters; Frequency conversion; Frequency locked loops; Phase locked loops; Voltage control; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1493953
