Title :
A 3.125 Gb/s limit amplifier with 42 dB gain and 1 μs offset compensation in 0.18 μm CMOS
Author :
Crain, Ethan ; Perrott, Michael
Author_Institution :
Microsystems Technol. Lab., MIT, Cambridge, MA, USA
Abstract :
An offset-compensation method uses a peak detector and multiple tap feedback to achieve 1000× improvement in settling time compared to prior art. Measurement results for a 3.125 Gb/s limit amplifier with 42 dB gain implemented in a 0.18 μm CMOS process are presented.
Keywords :
CMOS analogue integrated circuits; feedback amplifiers; integrated circuit design; optical communication equipment; peak detectors; 0.18 micron; 1 mus; 3.125 Gbit/s; 42 dB; CMOS process; SONET applications; amplifier gain; multiple tap feedback; offset compensation; peak detector; settling time; Bandwidth; Differential amplifiers; Diodes; Filters; Jitter; Optical signal processing; SONET; Switches; Switching circuits; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1493954
