Performance improvement of global interconnects using combined techniques of low swing transceiver and buffer insertion in nano technologies

Delay and power of the global interconnects are the most important parameters in the performance of VLSI circuits, particularly in nano scales. This paper presents a combined technique from a low swing transceiver and buffer insertion scheme. By this technique, we can reduce both the delay of global interconnects and also the power. In the other hand, we use a low swing transceiver to reduce the power of the interconnect and use the buffer insertion scheme for the interconnect between the driver and receiver to reduce the delay. Therefore, by this technique, we can reduce the powedelay product in nano scales.