Title :
A split-ADC architecture for deterministic digital background calibration of a 16b 1 MS/s ADC
Author :
McNeill, John ; Coln, Michael ; Larivee, Brian
Author_Institution :
Worcester Polytech. Inst., MA, USA
Abstract :
Self-calibration in fewer than 10,000 conversions is demonstrated in a 16b, 1 MS/s algorithmic ADC. A split-ADC architecture enables continuous digital background calibration. The analog sub-system of the ADC is implemented in 0.25 μm CMOS, consumes 105 mW and has a die size of 1.2×1.4 mm2.
Keywords :
CMOS integrated circuits; analogue-digital conversion; calibration; integrated circuit design; low-power electronics; 0.25 micron; 1.2 mm; 1.4 mm; 105 mW; 16 bit; algorithmic ADC; analog sub-system CMOS implementation; continuous digital background calibration; deterministic digital background calibration; die size; power consumption; self-calibration; split-ADC architecture; Bandwidth; Calibration; Circuit noise; Decorrelation; Least squares approximation; Linearity; Switched capacitor circuits; Switches; Switching circuits; Table lookup;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1493976
