DocumentCode
1671215
Title
A 50 MS/s (35 mW) to 1 kS/s (15 μW) power scaleable 10b pipelined ADC with minimal bias current variation
Author
Ahmed, Imran ; Johns, David
Author_Institution
Univ. of Toronto, Ont., Canada
fYear
2005
Firstpage
280
Abstract
A new opamp with a short power-on time is used in a 10b 1.5b/stage power scalable pipelined ADC in 0.18 μm CMOS. A current modulation technique is used so that as the power is varied from 15 μW (at 1 kS/s) to 35 mW (at 50 MS/s) the bias currents only increase by a factor of 50. The SNDR is 54 to 56 dB for all sampling rates.
Keywords
CMOS integrated circuits; analogue-digital conversion; electric current; integrated circuit design; integrated circuit measurement; low-power electronics; modulation; operational amplifiers; pipeline processing; signal sampling; 0.18 micron; 10 bit; 15 muW; 35 mW; CMOS power scalable pipelined ADC; SNDR; current modulation technique; minimal bias current variation; opamp power-on time; sampling rates; varied power bias currents; Costs; Delay; Energy consumption; Mirrors; Noise reduction; Pipelines; Production; Sampling methods; Time to market; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
0-7803-8904-2
Type
conf
DOI
10.1109/ISSCC.2005.1493978
Filename
1493978
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