Title :
Transistor level optimization of sub-pipelined AES design in CMOS 65nm
Author :
Alma´aitah, Abdallah ; Abid, Zine-Eddine
Author_Institution :
Electr. & Comput. Eng. Dept., Queen´´s Univ., Kingston, ON, Canada
Abstract :
Stage optimization of the hardware implementation of the popular encryption algorithms, the Advanced Encryption Standard (AES), is presented. The optimization, for lower power dissipation, is based on implementing the Multi Threshold CMOS (MTCMOS) technique in each of the AES stages. The critical paths are implemented using high performance gates based on high driving current transistors. For the optimized design, the Simulation results show about 10% reduction in power consumption compared to non optimized designs while maintaining the same throughput of 18Gbit/sec.
Keywords :
CMOS integrated circuits; cryptography; integrated circuit design; MTCMOS technique; advanced encryption standard; bit rate 18 Gbit/s; driving current transistors; encryption algorithms; hardware implementation; multithreshold CMOS technique; power dissipation; size 65 nm; stage optimization; sub-pipelined AES design; transistor level optimization; CMOS integrated circuits; CMOS technology; Encryption; Logic gates; Threshold voltage; Throughput; Transistors; Advance Encryption Standard (AES); Design optimization; Leakage current reduction; Multi-threshold CMOS (MTCMOS);
Conference_Titel :
Microelectronics (ICM), 2011 International Conference on
Conference_Location :
Hammamet
Print_ISBN :
978-1-4577-2207-3
DOI :
10.1109/ICM.2011.6177419
