Title :
Clock distribution on a dual-core, multi-threaded Itanium®-family processor
Author :
Mahoney, Patrick ; Fetzer, Eric ; Doyle, Bruce ; Naffziger, Sam
Author_Institution :
Intel, Fort Collins, CO, USA
Abstract :
Clock distribution on the 90 nm Itanium® processor, code-named Montecito, is detailed. A region-based active de-skew system reduces the PVT sources of skew across the entire die during normal operation. Clock vernier devices inserted at each local clock buffer allow up to a 10% clock-cycle adjustment via firmware or scan. The system supports a constantly varying frequency and consumes <25 W from the PLL to latch while providing <10 ps of skew across PVT.
Keywords :
microprocessor chips; multi-threading; phase locked loops; power consumption; synchronisation; 90 nm; Itanium processor; Montecito; clock distribution; clock vernier devices; clock-cycle adjustment; dual-core processor; firmware; local clock buffer; multi-threaded processor; region-based active de-skew system; Clocks; Delay lines; Design for disassembly; Frequency conversion; Phase locked loops; Program processors; Repeaters; Temperature; Voltage; Wire;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1493984
