Title :
A 90nm variable-frequency clock system for a power-managed Itanium®-family processor
Author :
Fischer, Tim ; Anderson, Ferd ; Patella, Ben ; Naffziger, Sam
Author_Institution :
Intel, Fort Collins, CO, USA
Abstract :
A clock-generation system delivers fixed- and variable-frequency clocks for adaptive power control on a 1.7 B-transistor dual-core CPU. Frequency synthesizers digitally divide a fixed-frequency PLL clock in 1/64th cycle steps using programmable voltage-frequency-converter loops. 1-cycle loop response tracks supply transients with adaptive modulation, improving CPU performance by over 10% compared to a fixed-frequency design.
Keywords :
adaptive control; adaptive modulation; frequency dividers; frequency synthesizers; microprocessor chips; phase locked loops; power control; 90 nm; CPU adaptive power control; adaptive modulation; clock-generation system; digital frequency dividers; fixed-frequency PLL clock; frequency synthesizers; loop response; power-managed processor; programmable voltage-frequency-converter loops; supply transient tracking; variable-frequency clock system; Adaptive control; Clocks; Digital modulation; Frequency synthesizers; Modulation coding; Phase locked loops; Power control; Programmable control; Tracking loops; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1493985
