Title :
Ultra-dynamic voltage scaling using sub-threshold operation and local voltage dithering in 90nm CMOS
Author :
Calhoun, Benton H. ; Chandrakasan, Anantha
Author_Institution :
MIT, Cambridge, MA, USA
Abstract :
Local voltage dithering combined with sub-threshold operation permits ultra-dynamic voltage scaling from 1.1 V to below 300 mV for a 90 nm CMOS adder test chip. Operating at 330 mV, it provides minimum energy per cycle with 9-times less energy than ideal shutdown for reduced-rate scenarios. Measurements characterize the minimum energy point across temperature.
Keywords :
CMOS logic circuits; adders; low-power electronics; 1.1 V; 300 mV; 330 mV; 90 nm; CMOS adder; UDVS; local voltage dithering; minimum energy per cycle; sub-threshold operation; ultra-dynamic voltage scaling; Adders; Circuit testing; Clocks; Dynamic voltage scaling; Frequency; Ring oscillators; Switches; Temperature; Voltage control; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1493988
