Sleep transistor circuits for fine-grained power switch-off with short power-down times

Author

Henzler, Stephan ; Nirschl, Thomas ; Skiathitis, Stylianos ; Berthold, Joerg ; Fischer, Juergen ; Teichmann, Philip ; Bauer, Florian ; Georgakos, Georg ; Schmitt-Landsiedel, Doris

Author_Institution

Tech. Univ. Munich, Germany

fYear

2005

Firstpage

302

Abstract

Fine-grained sleep transistor circuits are demonstrated with 0.12μm 16 b MAC (multiply-accumulate unit). Standby power is reduced by a factor of 5500 at 85°C with speed reduction of 5%. Charge recycling reduces the minimum sleep time by 25%. Dynamic power dissipation decreases by 16% activating a fraction of the switch in slow mode. Double switching inhibits power-on glitches and reduces current spikes by 38%.

Keywords

CMOS logic circuits; adders; field effect transistor switches; low-power electronics; multiplying circuits; 0.12 micron; 85 degC; CMOS; MAC; PMOS power-switches; charge recycling; current spike reduction; double switching; dynamic power dissipation decrease; fine-grained power switch-off; multiply-accumulate unit; parallel adder; power-on glitch inhibition; short power-down times; sleep transistor circuits; slow mode switch activation; standby power reduction; Adders; Circuit testing; Integrated circuit technology; Pipelines; Steady-state; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

0-7803-8904-2

Type

conf

DOI

10.1109/ISSCC.2005.1493989

Filename

1493989