• DocumentCode
    1671658
  • Title

    A loop-bandwidth calibration system for fractional-N synthesizer and ΔΣ-PLL transmitter

  • Author

    Akamine, Yukinori ; Kawabe, Manabu ; Hori, Kazuyuki ; Okazaki, Takao ; Tolson, Nigel ; Kasahara, Masumi ; Tanaka, Satoshi

  • Author_Institution
    Hitachi Ltd., Kokubunji, Japan
  • fYear
    2005
  • Firstpage
    314
  • Abstract
    A 0.25 μm BiCMOS fractional-N PLL with loop-bandwidth calibration is implemented in 3.3×3.3mm2. Using double-integration that integrates VCO output signal over the transient step response, the calibrated PLL achieves tuning accuracy of 2% with less than 2° rms phase error when used as a ΔΣ-PLL transmitter for GSM.
  • Keywords
    BiCMOS integrated circuits; UHF integrated circuits; calibration; cellular radio; phase locked loops; radio transmitters; voltage-controlled oscillators; ΔΣ-PLL transmitter; 0.25 micron; BiCMOS fractional-N PLL; GSM; VCO output signal; double integration; fractional-N synthesizer; loop-bandwidth calibration system; transient step response; Calibration; Charge pumps; Counting circuits; Field programmable gate arrays; Filters; GSM; Phase locked loops; Synthesizers; Transmitters; Voltage-controlled oscillators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-8904-2
  • Type

    conf

  • DOI
    10.1109/ISSCC.2005.1493995
  • Filename
    1493995
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1671658