All-digital PLL and GSM/EDGE transmitter in 90nm CMOS

Author

Staszewski, Robert Bogdan ; Wallberg, John ; Rezeq, Sameh ; Hung, Chih-Ming ; Eliezer, Oren ; Vemulapalli, Sudheer ; Fernando, Chan ; Maggio, Ken ; Staszewski, Roman ; Barton, Nathen ; Lee, Meng-Chang ; Cruise, Patrick ; Entezari, Mitch ; Muhammad, Khurra

Author_Institution

Texas Instruments, Dallas, TX, USA

fYear

2005

Firstpage

316

Abstract

A 1.2V 42mA all-digital PLL and polar transmitter for a single-chip GSM/EDGE transceiver is implemented in 90nm CMOS. It transmits GMSK with 0.5° rms phase error and achieves -165dBc/Hz phase noise at 20MHz offset, with 10 μs settling time. A digitally controlled 6dBm class-E PA modulates the amplitude and meets the EDGE spectral mask with 3.5% EVM.

Keywords

CMOS digital integrated circuits; UHF integrated circuits; UHF power amplifiers; cellular radio; data communication; digital control; digital phase locked loops; minimum shift keying; packet radio networks; radio transmitters; transceivers; 1.2 V; 10 mus; 42 mA; 90 nm; CMOS; EDGE spectral mask; GMSK; GSM/EDGE transmitter; all-digital PLL; class-E PA; digital control; polar transmitter; single-chip GSM/EDGE transceiver; CMOS analog integrated circuits; CMOS digital integrated circuits; CMOS process; Frequency modulation; GSM; IIR filters; Land mobile radio cellular systems; Phase locked loops; Radio transmitters; Varactors;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

0-7803-8904-2

Type

conf

DOI

10.1109/ISSCC.2005.1493996

Filename

1493996