Title :
A 10Gb/s CMOS adaptive equalizer for backplane applications
Author :
Gondi, Srikanth ; Lee, Jri ; Takeuchi, Daishi ; Razavi, Behzad
Author_Institution :
California Univ., Los Angeles, CA, USA
Abstract :
An equalizer employs reverse scaling and dual-loop adaptation to achieve a binary data rate of 10 Gbit/s. Realized in 0.13 μm CMOS technology, the circuit adapts to traces up to 30 inches on FR4 boards while consuming 25 mW from a 1.2 V supply.
Keywords :
CMOS integrated circuits; adaptive equalisers; radio receivers; 0.13 micron; 1.2 V; 10 Gbit/s; 25 mW; CMOS adaptive equalizer; FR4 boards; backplane applications; binary data rate; dual-loop adaptation; reverse scaling; Adaptive equalizers; Backplanes; Bandwidth; Boosting; CMOS technology; Cables; Circuits; Dielectric losses; Microelectronics; Resistors;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1494002
