DocumentCode :
1672293
Title :
Caching values in the load store queue
Author :
Nicolaescu, Dan ; Veidenbaum, Alex ; Nicolau, Alex
Author_Institution :
Dept. of Comput. Sci., California Univ., Irvine, CA, USA
fYear :
2004
Firstpage :
580
Lastpage :
587
Abstract :
The latency of an L1 data cache continues to grow with increasing clock frequency, cache size and associativity. The increased latency is an important source of performance loss in high-performance processors. The paper proposes to cache data utilizing the load store queue (LSQ) hardware and data paths. Using very little additional hardware, this inexpensive cache improves performance and reduces energy consumption. The modified load store queue "caches" all previously accessed data values going beyond existing store-to-load forwarding techniques. Both load and store data are placed in the LSQ and are retained there after a corresponding memory access instruction has been committed. It is shown that a 128-entry modified LSQ design allows an average of 51% of all loads in the SPECint2000 benchmarks to get their data from the LSQ. Up to 7% performance improvement is achieved on SPECint2000 with a 1-cycle LSQ access latency and 3-cycle L1 cache latency. The average speedup is over 4%.
Keywords :
cache storage; power consumption; queueing theory; L1 data cache latency; SPECint2000 benchmarks; caching values; energy consumption; load store queue; memory access instruction; store-to-load forwarding techniques; Clocks; Computer aided instruction; Computer science; Costs; Delay; Energy consumption; Frequency; Hardware; Performance loss; System performance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Modeling, Analysis, and Simulation of Computer and Telecommunications Systems, 2004. (MASCOTS 2004). Proceedings. The IEEE Computer Society's 12th Annual International Symposium on
ISSN :
1526-7539
Print_ISBN :
0-7695-2251-3
Type :
conf
DOI :
10.1109/MASCOT.2004.1348315
Filename :
1348315
Link To Document :
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