• DocumentCode
    1672311
  • Title

    A high throughput CMP process by using an Epic ECR directional ion source for intermetal dielectric

  • Author

    Wang, Justin K.

  • Author_Institution
    Lam Res. Corp., Fremont, CA, USA
  • fYear
    1995
  • Firstpage
    227
  • Lastpage
    229
  • Abstract
    Wafer fabrication technology is rapidly advancing toward four or five layers of metallization with geometries of 0.35 μm and smaller, aspect ratios of 3:1, and a requirement that the intermetal dielectric be globally planarized. Epic´s ECR Directional Ion Source combined with in situ sputter etch has been demonstrated repeatedly to fill 3:1 high aspect ratio gaps at 0.25 μm gap widths. The superior silane-based oxide does not absorb moisture over an extended period of time. The void-free gap fill in IMD provides the foundation for CMP because no slurry will be left in the IMD to cause reliability problems. The simultaneous deposition and etch step enhance the build-up of IMD over the lower valley on the device wafers. Thus IMD deposited by Epic exhibits a better planarity on the deposited wafer. The wafer topography after ECR deposition exhibits a unique surface that has only small peaks and step structures. These structures are easily removed by the CMP process. The increase in CMP throughput can be over 33%. The shortened polishing time helps the stability and repeatability of the CMP process
  • Keywords
    integrated circuit metallisation; integrated circuit reliability; polishing; sputter etching; surface topography; 0.25 to 0.35 micron; Epic ECR directional ion source; aspect ratios; global planarization; high throughput CMP process; in situ sputter etch; intermetal dielectric; lower valley; metallization; planarity; polishing time; reliability problems; void-free gap fill; wafer fabrication technology; wafer topography; Dielectrics; Fabrication; Geometry; Ion sources; Metallization; Moisture; Slurries; Sputter etching; Surfaces; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State and Integrated Circuit Technology, 1995 4th International Conference on
  • Conference_Location
    Beijing
  • Print_ISBN
    0-7803-3062-5
  • Type

    conf

  • DOI
    10.1109/ICSICT.1995.500072
  • Filename
    500072