• DocumentCode
    1672326
  • Title

    SE5 - SRAM design in the nanoscale era

  • Author

    Natarajan, Sreedhar ; Shubat, Alex

  • fYear
    2005
  • Firstpage
    366
  • Lastpage
    367
  • Keywords
    Circuit testing; Error analysis; Geometry; Leakage current; Logic devices; Logic testing; Paper technology; Random access memory; Solid state circuit design; Solid state circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-8904-2
  • Type

    conf

  • DOI
    10.1109/ISSCC.2005.1494021
  • Filename
    1494021
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1672326