Title :
Twill: A Hybrid Microcontroller-FPGA Framework for Parallelizing Single-Threaded C Programs
Author :
Gallatin, Doug ; Keen, Aaron ; Lupo, Chris ; Oliver, J.
Author_Institution :
Comput. Eng. Program, California Polytech. State Univ., San Luis Obispo, CA, USA
Abstract :
Increasingly System-On-A-Chip platforms which incorporate both microprocessors and re-programmable logic are being utilized across several fields ranging from the automotive industry to network infrastructure. Unfortunately, the development tools accompanying these products leave much to be desired, requiring knowledge of both traditional embedded systems languages like C and hardware description languages like Verilog. We propose to bridge this gap with Twill, a truly automatic hybrid compiler that can take advantage of the parallelism inherent in these platforms. Twill can extract long-running threads from single threaded C code and distribute these threads across the hardware and software domains to more fully utilize the asymmetric characteristics between processors and the embedded reconfigurable logic fabric. We show that Twill provides a significant performance increase on the CHStone benchmarks with an average 1.63 times increase over the pure hardware approach and an increase of 22.2 times on average over the pure software approach while in general decreasing the area required by the reconfigurable logic compared to the pure hardware approach.
Keywords :
C language; field programmable gate arrays; microcontrollers; multi-threading; parallel processing; system-on-chip; CHStone benchmarks; Twill; asymmetric characteristics; automatic hybrid compiler; automotive industry; embedded reconfigurable logic fabric; embedded systems languages; hardware description languages; hardware domains; hybrid microcontroller-FPGA framework; long-running threads; microprocessors; network infrastructure; parallelism; reprogrammable logic; single threaded C code; single-threaded C programs; software domains; system-on-a-chip; Field programmable gate arrays; Hardware; Hardware design languages; Message systems; Program processors; Runtime; Embedded Systems; Microcontroller-FPGA Hybrid Systems; Parallel Architecture;
Conference_Titel :
Parallel & Distributed Processing Symposium Workshops (IPDPSW), 2014 IEEE International
Conference_Location :
Phoenix, AZ
Print_ISBN :
978-1-4799-4117-9
DOI :
10.1109/IPDPSW.2014.17