An Isolation-Based Circuit Design for Soft Error Suppression

As the feature size of integrated circuits continues to shrink, deep sub-micro circuits are more susceptible to soft errors. In this paper, we propose a novel circuit design scheme, which can help increase the soft error immunity of sequential logics (such as SRAM cell and latch). The principle of the proposed circuit design is to build flexible isolation between soft-error sensitive nodes. The proposed scheme is applied to the design of various sequential logics at 70 nm technology. The simulation results show that the critical charge (the minimum charge to cause soft errors) can be increased by 1.98 times on average. Furthermore, combining together with multiple-V_th (MVT), multi-V_DD, and sizing techniques, the improvement of critical charge can add up to 237 times on average.