• DocumentCode
    1672433
  • Title

    An 8GHz floating-point multiply

  • Author

    Belluomini, Wendy ; Jamsek, Damir ; Martin, Andrew ; McDowell, Chandler ; Montoye, Robert ; Nguyen, Tuyet ; Ngo, Hung ; Sawada, Jun ; Vo, Ivan ; Datta, Ramyanshu

  • Author_Institution
    IBM, Austin, TX, USA
  • fYear
    2005
  • Firstpage
    374
  • Abstract
    The implementation of the mantissa portion of a floating-point multiply (54×54b) is described. The 0.124mm2 multiplier is implemented using limited switch dynamic logic and operates at speeds up to 8GHz in a 90nm SOI technology. The multiplier dissipates between 150mW and 1.8W as it scales between 2GHz and 8GHz.
  • Keywords
    floating point arithmetic; logic circuits; silicon-on-insulator; 150 mW to 1.8 W; 2 to 8 GHz; 90 nm; SOI technology; floating-point multiplier; limited switch dynamic logic; mantissa portion; Circuits; Clocks; Delay; Frequency; Latches; Logic; Pipelines; Switches; Testing; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-8904-2
  • Type

    conf

  • DOI
    10.1109/ISSCC.2005.1494025
  • Filename
    1494025
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1672433