Title :
A 110GOPS/W 16b multiplier and reconfigurable PLA loop in 90nm CMOS
Author :
Hsu, Steven ; Mathew, Sanu ; Anders, Mark ; Bloechel, Bradley ; Krishnamurthy, Ram ; Borkar, Shekhar
Author_Institution :
Intel, Hillsboro, OR, USA
Abstract :
A 16b 2´s-complement multiplier with a reconfigurable PLA control block is fabricated in a 90nm dual-Vt CMOS process and occupies 0.03mm2. It performs 1GHz single-cycle operations and dissipates 9mW to deliver 110GOPS/W at 1.3V, and is frequency scalable to 1.5GHz at 1.95V. PMOS sleep transistors enable an ultra low standby-mode power of 75 μW with wake-up time < 1 cycle.
Keywords :
CMOS logic circuits; MOSFET; low-power electronics; programmable logic arrays; reconfigurable architectures; 1 to 1.5 GHz; 1.3 V; 1.95 V; 2´s-complement multiplier; 75 muW; 9 mW; 90 nm; CMOS process; PMOS sleep transistors; reconfigurable PLA control block; reconfigurable PLA loop; ultra low standby-mode power; CMOS technology; Clocks; Delay; Encoding; Flip-flops; Noise measurement; Power measurement; Programmable logic arrays; Registers; Time measurement;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1494026
