Title :
A double-precision multiplier with fine-grained clock-gating support for a first-generation CELL processor
Author :
Kuang, J.B. ; Buchholtz, T.C. ; Dance, S.M. ; Warnock, J.D. ; Storino, S.N. ; Wendel, D. ; Bradley, D.H.
Author_Institution :
IBM, Austin, TX, USA
Abstract :
The feasibility of a fully integrated RF front-end using an above-IC BAW integration technique is demonstrated for WCDMA applications. The circuit has a voltage gain of 31.3dB, a noise figure of 5.3dB, an in-band IIP3 of -8dBm and IIP2 of 38dBm, with a total power consumption of 36mW. The BAW filter area is 0.45mm2 and the total circuit area including the BAW filter is 2.44mm2.
Keywords :
3G mobile communication; acoustic filters; bulk acoustic wave devices; clocks; radiofrequency integrated circuits; 31.3 dB; 36 mW; 5.3 dB; BAW filter; WCDMA applications; above-IC BAW integration; double-precision multiplier; fine-grained clock-gating support; first-generation CELL processor; fully integrated RF front-end; Capacitors; Circuits; Clocks; Delay; Hardware; Latches; Logic devices; Merging; Scalability; Wires;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1494027
