Title :
Modelling, Analysis and Design of Cascaded Forward and Interleaved Converter for Powering Future Microprocessors
Author :
Singh, Ravinder Pal ; Khambadkone, Ashwin M. ; Samudra, Ganesh S. ; Liang, Yung C.
Author_Institution :
Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore
Abstract :
The future microprocessors will operate at significantly lower voltages and demand much higher currents than the present generation microprocessors. They require voltage regulating modules (VRM) to provide the desired regulated power supply. In this paper, we present the requirements for the VRMs for future microprocessors and discuss the limitations of the existing topologies. Due to narrow duty ratio of single stage conversion, there is non-uniform distribution of losses. Thus a two-stage conversion comprising of an isolated stage as the front end and a phase-shifted interleaved converter as the backend is discussed. A small-signal model is derived for an interleaved converter, taking into account the asymmetry in the circuit elements. Finally a controller is designed for a cascaded system
Keywords :
DC-DC power convertors; cascade control; control system synthesis; microcomputers; network synthesis; voltage control; voltage regulators; cascaded forward converter; microprocessors; phase-shifted interleaved converter; regulated power supply; single stage conversion; voltage regulating modules; CMOS process; CMOS technology; Circuits; Clocks; Control systems; Frequency; Microprocessors; Power supplies; Topology; Voltage; DC-DC Converter; Forward Converter; Interleaved Converter; Voltage Regulating Module (VRM); two-stage;
Conference_Titel :
Power Electronics and Drives Systems, 2005. PEDS 2005. International Conference on
Conference_Location :
Kuala Lumpur
Print_ISBN :
0-7803-9296-5
DOI :
10.1109/PEDS.2005.1619725
