FPGA Redundancy Configurations: An Automated Design Space Exploration

With ever-decreasing CMOS transistor sizes, integrated circuits are becoming more and more susceptible to errors. A commonly used approach to improve the reliability of digital circuits is triple modular redundancy (TMR). TMR instantiates three copies of a circuit plus additional voter circuits to take majority decisions on the output values. Prior research has studied variations in TMR voting structures that bring about improvements in performance factors such as area utilization, power consumption and latency at the price of slight degradation in output reliability. In this paper, we extend previous studies by utilizing different redundancy configurations and voter-insertion algorithms to observe variation in these performance factors for FPGA designs. To maintain an automated tool flow for redundancy insertion into a digital design, we enhance the functionality of the previous BYU-LANL TMR tool to include alternative TMR and cascaded TMR redundancy configurations. Design space exploration experiments with different ISCAS circuit benchmarks show that the choice of an appropriate redundancy configuration and voter-insertion algorithm has a strong impact on optimizing performance factors. To support a designer with selecting a redundant implementation, we present a design space exploration tool flow that takes a circuit as input and identifies Pareto-optimal implementations with respect to the four objectives reliability level, utilized FPGA area, latency and dynamic power consumption.