Xilinx FPGA implementation of an image classifier for object detection applications

This paper describes an FPGA and distributed RAM architecture for an image classifier, implementing object classification stages of an object detection system. The system offers significant performance increase over current programmable DSP-based implementations. The paper shows that the considerable performance improvement using the FPGA solution results from the availability of high I/O resources and pipelined architecture. It also illustrates the suitability of an FPGA solution for tasks (such as real-time video processing) that have a large data throughput and require complex algorithmic manipulations. The system has been implemented using the RC1000-PP Virtex FPGA-based development platform and Handel-C hardware description language