DocumentCode
1672852
Title
A 15mW 3.125GHz PLL for serial backplane transceivers in 0.13 μm CMOS
Author
Parker, James F. ; Weinlader, Daniel ; Sonntag, Jeff L.
Author_Institution
Synopsys, Hillsboro, OR, USA
fYear
2005
Firstpage
412
Abstract
A 3.125GHz PLL fabricated in a 0.13 μm CMOS process in a area of 0.064mm2 is described. The PLL uses an architecture optimized for low noise, low power and small die area. In steady-state operation, the PLL forces the up and down currents in the charge pump to match one another. The total measured jitter is 1.3ps rms when operating at 3.125GHz and the chip consumes 15mW.
Keywords
CMOS integrated circuits; low-power electronics; phase locked loops; timing jitter; transceivers; 0.13 micron; 15 mW; 3.125 GHz; CMOS; PLL; charge pump; current matching; die area; jitter; low noise architecture; low power architecture; serial backplane transceivers; steady-state operation; Backplanes; Charge pumps; Clocks; Jitter; Open loop systems; Phase locked loops; Ring oscillators; Transceivers; Voltage control; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
0-7803-8904-2
Type
conf
DOI
10.1109/ISSCC.2005.1494044
Filename
1494044
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