Title :
A low-jitter wideband multiphase PLL in 90nm SOI CMOS technology
Author :
Kossel, Marcel ; Buchmann, Peter ; Menolfi, Christian ; Morf, Thomas ; Toifl, Thomas ; Schmatz, Martin
Author_Institution :
IBM, Ruschlikon, Switzerland
Abstract :
A multiphase PLL, implemented in 90nm SOI CMOS, covers a frequency range from 4.3 to 7.4GHz at a supply voltage of 1V. The ring oscillator-based PLL shows an in-band phase noise of up to -113dBc/Hz at 1 MHz offset and a supply noise rejection of 0.23%delay/%supply due to the rigorous application of CML-type circuit topologies combined with replica biasing.
Keywords :
CMOS integrated circuits; current-mode logic; microwave oscillators; network topology; phase locked loops; silicon-on-insulator; timing jitter; 1 V; 4.3 to 7.4 GHz; 90 nm; CML-type circuit topologies; SOI CMOS technology; in-band phase noise; low-jitter wideband multiphase PLL; replica biasing; ring oscillator; wideband multiphase PLL; CMOS technology; Charge pumps; Circuits; Delay; Filters; Phase locked loops; Transmitters; Tuning; Voltage; Wideband;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1494045
