Title :
An ultra-low-power fast-lock-in small-jitter all-digital DLL
Author :
Wang, Jinn-Shyan ; Wang, Yi-Ming ; Chen, Chin-Hao ; Liu, Yu-Chia
Author_Institution :
Chung-Cheng Univ., Chia-Yi, Taiwan
Abstract :
Using binary-weighted differential-delay cells and an asynchronous binary search circuit, the proposed 1.0V 0.25 μm all-digital DLL achieves nearly 2 orders of magnitude reduction in power consumption, a 36% reduction in jitter, and a 33% reduction in locking cycles, compared to conventional fast-lock mixed-mode DLL.
Keywords :
asynchronous circuits; delay lock loops; low-power electronics; power consumption; timing jitter; 0.25 micron; 1 V; asynchronous binary search circuit; binary-weighted differential-delay cells; fast-lock-in all-digital DLL; locking cycles; power consumption; small-jitter all-digital DLL; ultra-low-power all-digital DLL; Analog circuits; Clocks; Counting circuits; Delay effects; Delay lines; Detectors; Energy consumption; Jitter; Phase detection; Switches;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1494049
