Simultaneous Optimization of Performance and Thermal Effects Based on Two-stage Microarchitectural Floorplanning

The trends in VLSI design go toward increased component integrated density and higher power consumption. The thermal management plays a prominent role in recent years. The maximum temperature of a block in a chip depends, however, not only on its own power density, but also on the power density of the adjacent blocks. Consequently, the layout of architectural blocks, or a particular floorplan selected for a given chip, can affect the maximum temperature of the chip considerably. Our floorplanner simultaneously considers high performance, thermal reliability, area, and interconnect length and provides various tradeoff points. We use two-stage optimization in microarchitectural floorplanning so that the trade-off between performance and the thermal effects can be well controlled. An Alpha microprocessor is used as an example to demonstrate the effect of our floorplanner. The experimental results show that our floorplanner is stable which can simultaneously optimize the performance and temperature of the design.