Area optimized CMOS layouts of a 50 Gb/s low power 4:1 multiplexer

In this work, novel layouts of a 4:1 CMOS transmission gate multiplexer are presented. The proposed layouts are realized by following the design rules for 45 nm and 90 nm CMOS processes, with a supply voltage of 1.2 V. Both layouts are designed using two different routing strategies - using only one metal layer, and using two metal layers. The power dissipation and area are noted and compared in all four cases. It is observed that layouts utilizing two metal layers have reduced area but augmented cost of fabrication. The multiplexer layout, using two metal layers for routing, generates an output bit rate as high as 50 Gb/s, without any erroneous bit, in case of 90 nm technology and occupies an area of 8.91 μm²; dissipating 55.966 μW of power. The output bit rate remains same for 45 nm process, with zero bit error, a power consumption of 33.713 μW and an area of 2.45 μm². The multiplexer continues to operate till 60 Gbps with a BER of 1/8. The areas occupied by these layouts are the lowest encountered in the authors´ literature survey.