A Watermarking Technique for Hard IP Protection in Full-custom IC Design

Intellectual property (IP) block reuse is essential for facilitating the design process of system-on-a-chip (SOC). However, sharing IP blocks in today´s competitive market poses significant high security risks. Recently, digital watermarking emerged as a candidate solution for copyright protection of IP blocks. In this paper, a new watermarking technique is proposed in full-custom IC design. We develop the technique for hard IP protection based on adjusting the transistors to fit the watermark value. This technique is compatible with the existing IC design flow. The paper describes the outline of the technique, overviews the schemes used in its components, and reports experimental results.