Title :
High speed self biased current sense amplifier for low power CMOS SRAM´s
Author :
Bashir, Mudasir ; Patri, Sreehari Rao ; Krishnaprasad, K.S.R.
Author_Institution :
Dept. of ECE, NIT, Warangal, India
Abstract :
Sense amplifiers are one of the important circuits in the CMOS memories as they have a greater impact on the access time and power dissipation of memory cells. The current-mode sense amplifiers have improved the access time as well as power dissipation to a large extent when compared to voltage-mode sense amplifiers, thus resulting in making the memories compatible with the high speed CMOS technologies. In this paper, a new topology of current-mode sense amplifiers is introduced which overcomes the imperfections associated with the conveyer based current-mode sense amplifiers. The circuit has resulted in a low sense delay of 596.6 psecs and power dissipation of 0.87uW and in the end the effect of bit-line capacitances on sense delay, power supply and temperature on power dissipation is calculated.
Keywords :
CMOS memory circuits; SRAM chips; amplifiers; capacitance; CMOS memories; access time; bit-line capacitances; conveyer based current-mode sense amplifiers; high speed CMOS technologies; high speed self biased current sense amplifier; low power CMOS SRAM; memory cells; power dissipation; sense delay; CMOS integrated circuits; Capacitance; Delays; Power dissipation; Random access memory; Sensors; Transistors; Bitline capacitance; Current Conveyer; SRAM cell; Sense Amplifiers; Sense Delay;
Conference_Titel :
VLSI Design and Test (VDAT), 2015 19th International Symposium on
Conference_Location :
Ahmedabad
Print_ISBN :
978-1-4799-1742-6
DOI :
10.1109/ISVDAT.2015.7208057
