Crosstalk Minimization Method for System-on-Chip

The crosstalk caused by the coupling capacitance is a major source of load and delay faults in ultra-deep submicron system on chip. In this paper, a crosstalk minimization design for the system-on-chip is presented. We first use a divide-and-conquer method to rearrange wire-segments such that the coupling length can be minimized. Next, the space between adjacent tracks is adjusted by using a quadratic programming method. We have implemented the proposed design on the AMBA-based SoC platform and provided experimental results to demonstrate the effectiveness of the method.