A Sequential Circuit Partitioning Algorithm for Dynamically Reconfigurable FPGAs

In this paper, we present a sequential circuit partitioning algorithm to minimize the number of registers for dynamically reconfigurable FPGAs. The algorithm is performed on our specific graph model and divided into two phases: 1) the labeling phase and 2) the minimizing cost phase. We first use as soon as possible and as late as possible algorithms to assign nodes so that the precedence constraints are satisfied. Then, some nodes are adjusted or replicated according to several proposed methods to minimize the number of registers. Experimental results demonstrate the effectives of our algorithms.