Title :
Super-scale architecture enhancement of LEON3 core for DSP application
Author :
Mehta, Jagrat ; Darji, Anand ; Ram, T.V.S. ; Arora, Rajat
Author_Institution :
Electron. & Commun. Eng. Dept., Charusat Univ., Changa, India
Abstract :
There are two main directions in the development of modern microprocessor architectures used for System on Chip: low Power consumption and high performance. The paper presents the method for enhancing LEON3 processor IP core with superscalar ability for high-performance and low-power systems. As compared to the original LEON3 IP core, the proposed super scalar design executes is up to two instructions per cycle with only one third area increase. Application to perform FFT/IFFT is developed and tested using enhanced architecture of LEON3 IP core for superscalar processing. Performance enhancement of LEON3 core is also compared with Very Long Instruction Word (VLIW) processor and Silicon labs application note. The enhanced SoC is synthesized and implemented on Actel FPGA ProASIC3E. The area, power and timing comparison is shown. Approximately 33% enhancement in execution time is obtained due to the proposed super scaling scheme for LEON3 IP core.
Keywords :
digital signal processing chips; fast Fourier transforms; low-power electronics; silicon; system-on-chip; DSP; IFFT; IP core; LEON3; Si; Silicon labs; SoC Actel FPGA ProASIC3E; low power consumption; low-power systems; microprocessor architectures; super-scale architecture enhancement; superscalar processing; system on chip; very long instruction word processor; Clocks; Field programmable gate arrays; IP networks; Power demand; Registers; Silicon; VLIW; Cache; FFT; Pipeline; Register File; Super-scalar;
Conference_Titel :
VLSI Design and Test (VDAT), 2015 19th International Symposium on
Conference_Location :
Ahmedabad
Print_ISBN :
978-1-4799-1742-6
DOI :
10.1109/ISVDAT.2015.7208067
