Author :
Iida, M. ; Kuroda, N. ; Otsuka, H. ; Hirose, M. ; Yamasaki, Y. ; Ohta, K. ; Shimakawa, K. ; Nakabayashi, T. ; Yamauchi, H. ; Sano, T. ; Gyohten, T. ; Maruta, M. ; Yamazaki, A. ; Morishita, F. ; Dosaka, K. ; Takeuchi, M. ; Arimoto, K.
Abstract :
An embedded DRAM macro in a logic compatible 90nm CMOS process is designed with low-noise core architecture and high-accuracy post-fabrication tuning. With a 5fF/cell capacitance, a 61% improvement of sensing accuracy enables 322MHz random-cycle operation and reduces data retention power to 60 μW.
Keywords :
CMOS memory circuits; DRAM chips; circuit tuning; embedded systems; 322 MHz; 5 fF; 60 muW; 90 nm; CMOS process; data retention power; high-accuracy sensing; low-noise core architecture; post-fabrication tuning; random-cycle embedded DRAM; Capacitors; Circuit noise; Costs; Coupling circuits; Delay; Metal-insulator structures; Noise cancellation; Noise reduction; Random access memory; Signal to noise ratio;
