DocumentCode
1673376
Title
A 400MHz random-cycle dual-port interleaved DRAM with striped-trench capacitor
Author
Shirahama, M. ; Agata, Y. ; Kawasaki, T. ; Nishihara, R. ; Abe, W. ; Kuroda, N. ; Sadakata, H. ; Uchikoba, T. ; Takahashi, K. ; Egashira, K. ; Honda, S. ; Miura, M. ; Hashimoto, S. ; Kikukawa, H. ; Yamauchi, H.
Author_Institution
Matsushita, Nagaokakyo, Japan
fYear
2005
Firstpage
462
Abstract
We present a 400MHz random-cycle dual-port interleaved 1.5V DRAM macro with fully sense-signal-loss compensating technologies based on noise-element breakdowns, a striped trench capacitor cell and write-before-sensing by a decoded write-bus circuit technique. The IC is implemented in a 0.15 μm CMOS logic process.
Keywords
CMOS logic circuits; CMOS memory circuits; DRAM chips; 0.15 micron; 1.5 V; 400 MHz; CMOS logic IC; decoded write-bus circuit; dual-port interleaved DRAM; fully sense-signal-loss compensating technologies; noise-element breakdowns; random-cycle DRAM; striped trench capacitor cell; write before sensing; CMOS process; Capacitance; Capacitors; Decoding; Equalizers; Low-noise amplifiers; Noise level; Noise reduction; Random access memory; Signal processing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
0-7803-8904-2
Type
conf
DOI
10.1109/ISSCC.2005.1494069
Filename
1494069
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