Title :
A 18 mW triple 2 GHz CMOS PLL for 3G mobile systems with -113 dBc/Hz GSM in-band phase noise and dual-port GMSK modulation
Author :
Guenais, Mikaël ; Colomines, Stéphane ; Beaulaton, Hugues ; Gorisse, Philippe
Author_Institution :
Motorola Semicond. Product Sector, Toulouse, France
Abstract :
A PLL for 3G systems achieves -113-dBc/Hz close-in phase noise in the GSM Band and consumes 18 mW (2 mA for the 5 V charge-pump and 4mA under 1.875 Volts for the remaining blocks). The GMSK Dual-Port modulation system achieves 1.2° rms phase error and a noise level of -67dBc at 400 kHz offset from carrier in a 30 kHz BW. Three PLLs are integrated on the same die and are synchronized to avoid crosstalk issues.
Keywords :
3G mobile communication; CMOS integrated circuits; UHF integrated circuits; cellular radio; minimum shift keying; phase locked loops; phase noise; synchronisation; 18 mW; 2 GHz; 3G mobile system; GSM in-band phase noise; charge pump; dual-port GMSK modulation; synchronization; triple CMOS PLL; Charge pumps; Circuits; Crosstalk; GSM; Noise cancellation; Phase locked loops; Phase modulation; Phase noise; Signal to noise ratio; Voltage;
Conference_Titel :
Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 IEEE
Print_ISBN :
0-7803-7694-3
DOI :
10.1109/RFIC.2003.1213922
