Title :
An AND-type match-line scheme for energy-efficient content addressable memories
Author :
Wang, Jinn-Shyan ; Li, Hung-Yu ; Chen, Chia-Cheng ; Yeh, Chingwei
Author_Institution :
Nat. Chung Cheng Univ., Chai-Yi, Taiwan
Abstract :
An AND-type match-line scheme is fabricated in a 0.18 μm 1.8V CMOS process. The 256×128b CAM achieves a faster search time and a 20% energy reduction compared with NOR designs. This AND-type circuit has a search time of 1.75ns with an energy of 0.57fJ/bit/search.
Keywords :
CMOS memory circuits; content-addressable storage; logic gates; 0.18 mm; 1.8 V; 128 bit; AND-type match-line scheme; CAM; CMOS process; energy reduction; energy-efficient content addressable memories; search time; Associative memory; CADCAM; CMOS process; Cams; Clocks; Computer aided manufacturing; Energy efficiency; Logic design; Stacking; Switching circuits;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1494070
